Title :
Analysis and results of net coupling within a high performance microprocessor
Author :
Dansky, A.H. ; Smith, Howard H. ; Williams, P.M.
Author_Institution :
Data Syst. Div., IBM Corp., Poughkeepsie, NY
Abstract :
The trends in CMOS chip design have all been converging to worsen coupling between horizontally and vertically adjacent wires. The coupling between on chip wires can cause two different types of problems, namely, functional fails due to the induced coupled noise voltage, and changes in delay due to the changes in load capacitance caused by switching the activity of adjacent wires. A methodology based on closed form expressions is applied to predict noise and timing impact due to line to line coupling. Statistical results for a S/390 microprocessor are shown for over 20,000 nets
Keywords :
CMOS digital integrated circuits; delays; integrated circuit design; integrated circuit metallisation; microprocessor chips; timing; wiring; CMOS chip design; S/390 microprocessor; closed form expressions; delays; functional fails; high performance microprocessor; horizontally adjacent wires; line coupling; load capacitance; net coupling; on chip wires; timing; vertically adjacent wires;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting
Conference_Location :
Napa, CA
Print_ISBN :
0-7803-3514-7
DOI :
10.1109/EPEP.1996.564770
