DocumentCode :
3273916
Title :
A Novel Self-aligned Si-wire Flash Memory Featuring Multi-bit/cell Operation, Fast Edge +FN Erase, and Over-erasure Immunity
Author :
Hsueh, M.H. ; Shih, Y.H. ; Wu, M.D. ; Hsiao, W.M. ; Lu, C.P. ; Wu, C.W. ; Hsieh, J.Y. ; Lai, E.K. ; Hsieh, K.Y. ; Liu, Rich ; Lu, Chih-Yuan
Author_Institution :
Macronix Int. Co., Ltd, Hsinchu
fYear :
2007
fDate :
26-30 Aug. 2007
Firstpage :
52
Lastpage :
53
Abstract :
We present a new memory device using two self-aligned silicon wires for charge storage. Programming is by channel hot electron injection, and a large 2nd bit VT window ( >3 V) for multi-bit/cell operation is demonstrated. Erasing is by edge-enhanced +FN tunneling. Both program and erase operations can be performed at < 10 mus and the device is intrinsically immune to over-erasure. This new Si-wire device shows small program disturbance, small cycling-induced degradation, and adequate retention performance. This new device has all the benefits of nanocrystal device but is readily made by standard CMOS process and without the Coulomb blockade limitation. It is also more scalable than conventional floating gate devices.
Keywords :
CMOS memory circuits; flash memories; nanostructured materials; silicon; tunnelling; wires (electric); CMOS process; Si; cell operation; channel hot electron injection; charge storage; cycling-induced degradation; edge-enhanced +FN tunneling; multibit operation; nanocrystal device; over-erasure immunity; program operation; self-aligned silicon wires; CMOS process; Capacitance; Channel hot electron injection; Degradation; Flash memory; Nanocrystals; Nonvolatile memory; Silicon; Tunneling; Wires; flash memory; nanocrystal memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0753-2
Electronic_ISBN :
1-4244-0753-2
Type :
conf
DOI :
10.1109/NVSMW.2007.4290577
Filename :
4290577
Link To Document :
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