Air-Gap Application and Simulation Results for Low Capacitance in 60nm NAND Flash Memory

Author

Kim, Sukjoong ; Cho, Wheewon ; Kim, Junggeun ; Lee, Byungseok ; Park, SungKi

Author_Institution

Hynix Semicond. Inc., Kyoungki-do

fYear

2007

fDate

26-30 Aug. 2007

Firstpage

54

Lastpage

55

Abstract

In IMD study Rs reduction and better uniformity as well as lower capacitance were achieved in 60 nm 2 Giga Bit NAND flash memory. It alos fabricated 70 % air-gap of gate and calculated interference reduction in 45 nm device when it was applied throughout simulation. It is sure that we should apply this air-gap process to future device in order to meet device property of cell Vt shift and capacitance.

Keywords

NAND circuits; flash memories; logic gates; In IMD study Rs reduction and better uniformity as well as lower capacitance were achieved in 60 nm 2 Giga Bit NAND Flash Memory. We fabricated 70 % air-gap of gate and calculated interference reduction in 45 nm device when it was applied throughout simulation. We are sure that we should apply this air-gap process to future device in order to meet device property of cell Vt shift and capacitance; NAND flash memory; air-gap application; interference reduction; low capacitance; size 45 nm; size 60 nm; Air gaps; Capacitance measurement; Dielectric constant; Dielectric materials; Dielectric measurements; Electric variables measurement; Interference; Research and development; Sputtering; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE

Conference_Location

Monterey, CA

Print_ISBN

1-4244-0753-2

Electronic_ISBN

1-4244-0753-2

Type

conf

DOI

10.1109/NVSMW.2007.4290578

Filename

4290578