Title :
Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter
Author :
Kinoshita, K. ; Tsunoda, K. ; Sato, Y. ; Noshiro, H. ; Yamazaki, Y. ; Fukano, T. ; Yagaki, S. ; Aoki, M. ; Sugiyama, Y.
Author_Institution :
Fujitsu Lab. LTD., Atsugi
Abstract :
In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of Ireset by imposing current compliance Icomp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of Icomp dependence of lreset for Icomp < 1 mA and Ireset ap Icomp was observed for 150 muA les Icomp les950 muA.
Keywords :
CMOS integrated circuits; current limiters; nickel compounds; platinum; random-access storage; CMOS technology; NiO; NiO-ReRAM test circuits; Pt; cell transistor; current compliance; current limiter; reset current; size 0.18 mum; stray capacitance; CMOS technology; Capacitance; Circuit testing; Current limiters; Flash memory; Joining processes; Monitoring; Read-write memory; Sputtering; Voltage;
Conference_Titel :
Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0753-2
Electronic_ISBN :
1-4244-0753-2
DOI :
10.1109/NVSMW.2007.4290583
