Effect of organic package core via pitch reduction on power distribution performance

Advances in CMOS technology continue to provide increased circuit density and performance at a lower cost. Die size and cost can be further reduced for I/O limited applications by shrinking the area array flip-chip (C4) pad pitch. These advances continue to drive package ground rule improvements to efficiently distribute signal and power while reducing cost. One such groundrule for organic build-up packages is the core via pitch. Core via pitch reduction can significantly improve the package power distribution and signal escape. This paper presents the package design tradeoffs for core via pitch reduction to support a 90nm 9.3mm ASIC die using a 150μm full area array C4 pitch. The impact of core via pitch on power distribution performance, wireability, and cost will be presented, including electrical modeling and simulation results. Design trade-offs to optimize both the chip and package are presented, including die C4 pad pitch and depth versus module cost and performance.