Title :
Constrained collapse solder joint formation for wafer-level-chip-scale packages to achieve reliability improvement
Author :
Patwardhan, V. ; Nguyen, H. ; Zhang, L. ; Kelkar, N. ; Nguyen, L.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
Wafer-level-chip-scale-packages (WLCSP) are rapidly proving to be the package of choice for portable electronics applications. National Semiconductor´s micro SMD package family has been a front-runner in the development of this package type. These packages have a proven reliability in the lower pin-count range (up to 36 I/O) when used in conjunction with standard surface mount assembly (SMT). However, extending this technology to higher pin-counts is a significant challenge. Since the preferred assembly method is to not employ an additional underfill step after reflow soldering, the options available to enhance the package reliability are limited. Several options including a pre-applied epoxy layer that will flow and form the underfill layer during solder reflow are under investigation as a potential solution. This approach has constraints in terms of compatibility with flux type used and the reflow profile used. Another approach involves creating a non-reflowable underfill layer. This is the approach described in this paper, and it has proven to work with all commercial assembly processes and to all extents and purposes is transparent to the surface mount assembly method used. This approach is based on the creation of an epoxy layer in either a film or paste layer form that acts as a layer surrounding and partially submerging the solder bumps. This layer achieves two results that directly impact the reliability of the WLCSP assembly. The primary advantage is the increase in solder joint height achieved, which improves the fatigue life when subjected to thermal excursions. The other major advantage is that with the solder bump being constrained from collapsing completely, the angle of wetting formed on the die side is increased, resulting in a more ´cylindrical´ or barrel-shaped joint rather than a shape like a truncated sphere. Finite element modeling (P. Borgesen et al., IEEE Trans. on Comp., Hybrids, and Manuf. Tech., vol. 16, no. 3, pp. 272-283) has also borne out that a higher wetting angle results in higher reliability. There also appears to be an interaction between the pre-applied underfill layer thickness and the reliability of the outermost solder joint, which itself depends on the bump matrix size. A higher stand-off may not necessarily translat- e to a higher reliability due to this interaction effect.
Keywords :
assembling; chip scale packaging; encapsulation; finite element analysis; integrated circuit modelling; integrated circuit testing; plastic packaging; polymer films; reflow soldering; surface mount technology; SMT; WLCSP; WLCSP assembly; assembly processes; barrel-shaped joint; bump matrix size; constrained collapse solder joint formation; epoxy layer; fatigue life; finite element modeling; flux compatibility constraints; micro SMD package; nonreflowable underfill layer; outermost solder joint reliability; package pin-count; package reliability; partially submerged solder bumps; portable electronics; pre-applied epoxy layer; preferred assembly method; reflow profile constraints; reflow soldering; reliability; solder bump; solder joint height; stand-off height; standard surface mount assembly; thermal excursions; underfill layer; underfill layer thickness; underfill step; wafer-level-chip-scale packages; wetting angle; Assembly; Chip scale packaging; Electronics packaging; Fatigue; Reflow soldering; Semiconductor device packaging; Semiconductor device reliability; Silicon; Surface-mount technology; Wafer scale integration;
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
DOI :
10.1109/ECTC.2004.1320310