Improved FFSBM algorithm and its VLSI architecture for variable block size motion estimation of H.264

The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden. The FFSBM (fast full search block matching) algorithm has been proposed to reduce the complexity. This paper proposes an improved FFSBM to adaptively reduce the complexity of FFSBM according to the degree of motion activity. A modular 2-D VLSI architecture to implement the improved algorithm is also proposed, the size of the PE array is carefully selected to reduce the gate count. Experimental result shows that this algorithm-hardware co-design gives better area/throughput tradeoff than the existing ones and is a proper solution for H.264´s variable block size motion estimation.