Title :
Low Complexity Bit-Parallel Multiplier for a Class of Finite Fields
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON
Abstract :
This short paper summarizes our recent results on construction of low-complexity bit-parallel finite field multiplier using polynomial basis. The complexity and time delay of the proposed multipliers are lower than those of the similar proposals.
Keywords :
computational complexity; delays; multiplying circuits; finite field multiplier; low complexity bit-parallel multiplier; polynomial basis; time delay; Arithmetic; Concurrent computing; Delay effects; Design optimization; Elliptic curve cryptography; Galois fields; Logic; Polynomials; Proposals; Very large scale integration;
Conference_Titel :
Communications, Circuits and Systems Proceedings, 2006 International Conference on
Conference_Location :
Guilin
Print_ISBN :
0-7803-9584-0
Electronic_ISBN :
0-7803-9585-9
DOI :
10.1109/ICCCAS.2006.285197
