Low-cost, wafer level underfilling and reliability testing of flip chip devices

Wafer level underfilling of flip-chip devices offers great potential for high volume packaging at low cost. However, to date, few methods of wafer level underfilling have offered the potential for high assembly yield and high reliability. In this paper, we present a new process technology together with new materials systems for wafer level underfilling of flip-chip devices. This approach utilizes encapsulation of wafers with multiple material layers that are deposited onto an integrated circuit at the wafer level. The enhanced, solder-bumped wafer is then diced into fully encapsulated chips that can be flip-chip attached to printed circuit boards. The advantage of this process is that it requires little additional capital expenditure, yet results in high yield, high reliability assemblies.