DocumentCode :
3274250
Title :
Physical Understanding of SANOS Disturbs and VARIOT Engineered Barrier as a Solution
Author :
Furnemont, Arnaud ; Rosmeulen, M. ; Cacciato, A. ; Breuil, L. ; De Meyer, K. ; Maes, Hannes ; Van Houdt, J.
Author_Institution :
IMEC, Leuven
fYear :
2007
fDate :
26-30 Aug. 2007
Firstpage :
94
Lastpage :
95
Abstract :
Both read and program disturb sensitivity are identified to be major drawbacks for nitride-based NAND Flash arrays. The crucial aspects to understand the disturbs are the injection of electrons at low fields through the bottom oxide, and the tunneling through the top oxide during programming. These results are exploited to identify possible improvements of the device. A VARIOT engineered barrier is proposed to replace the bottom oxide layer in order to significantly reduce the disturb problem.
Keywords :
NAND circuits; flash memories; SONOS-type flash memories; VARIOT engineered barrier; electrons injection; nitride-based NAND flash arrays; Electrons; Flash memory; High K dielectric materials; High-K gate dielectrics; Leakage current; Low voltage; Performance evaluation; SONOS devices; Threshold voltage; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0753-2
Electronic_ISBN :
1-4244-0753-2
Type :
conf
DOI :
10.1109/NVSMW.2007.4290596
Filename :
4290596
Link To Document :
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