Title :
Symmetric semi-floating-gate pseudo differential pair for low-voltage analog design
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present a symmetric ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250 mV. Simulated data for 90 nm CMOS process is included.
Keywords :
CMOS analogue integrated circuits; MOSFET; clocks; differentiating circuits; integrated circuit design; low-power electronics; CMOS process; current level; low-voltage analog design; nMOS clocked semi floating-gate transistor; pMOS clocked semi floating-gate transistor; size 90 nm; symmetric pseudo differential pair; ultra low-voltage pseudo differential pair; voltage 250 mV; Analog circuits; CMOS analog integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Low voltage; MOS devices; MOSFETs; Threshold voltage;
Conference_Titel :
NORCHIP, 2009
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-4310-9
Electronic_ISBN :
978-1-4244-4311-6
DOI :
10.1109/NORCHP.2009.5397850
