M5 based EDGE architecture modeling

EDGE (Explicit Data Graph Execution) architectures, a class of architectures distinct from traditional RISC and CISC architectures, have advantages that align well with current technology trends such as power limitations and the need for adaptive exploitation of parallelism. To better understand the architectural and microarchitectural design spaces of EDGE architectures, we have developed a flexible M5-based simulator for EDGE architectures. m5_edge includes a general high-level timing model and ISA support of one specific EDGE ISA. The high-level timing model is not designed to target a specific implementation but common characteristics of EDGE architectures, permitting faster development of a range of microarchitectures. The M5 infrastructure was used because of its high functionality and performance fidelity. The specific EDGE ISA we support is the TRIPS ISA, due to its well-specified ISA and relatively mature compiler. m5_edge can execute binaries generated by the TRIPS toolchain and provides a high-level simulation template for EDGE architectures. Our experimental results show that the difference in execution cycles of m5_edge is within 11% on average, compared to the cycle-accurate simulator provided by the TRIPS group. Thus, m5_edge benefits from both the flexible infrastructure of M5 and acceptable model accuracy, while maintaining both reasonable simulation speed and the ability to quickly explore EDGE-based microarchitectural design spaces.