Numerical modeling of a clock distribution network for a superconducting multichip module

As supercomputers continue to move towards more powerful processors and parallelization, fast switching structures to route data signals between processors and shared memory become essential, and in fact, may be a primary limiting factor in overall computational throughput. The fast switching network under consideration in this paper is a “crossbar” switch employing superconducting Josephson Junction (JJ) and Multichip Module (MCM) technology. This paper focuses on the design and simulation of the clock distribution network, located within the MCM, that will provide the necessary timing mechanism for data signals traveling through the crossbar switch