A High-Speed Network Interface Design for Packet-Based NoC

Author

Yong-Long Lai ; Yang, Shyue-Wen ; Sheu, Ming-hwa ; Hwang, Yin-Tsung ; Tang, Hui-Yu ; Huang, Pin-Zhang

Author_Institution

Grad. Sch. of Eng. Sci. & Technol., Nat. Yunlin Univ. of Sci. & Technol., Douliou

Volume

4

fYear

2006

fDate

25-28 June 2006

Firstpage

2667

Lastpage

2671

Abstract

In this paper, we propose an interface design which supports serial-link packet-based transmission model for network-on-chip application The interface function consists of packet construction, flow control, error detect, re-transmission mechanism, data scrambler and 8b/10b transformation. The whole function is partitioned into three layers and designed as a peer-to-peer architecture. Every layer can be further divided into a transmitting portion that processes outbound traffic and a receiving portion that processes inbound traffic. We also simulate the buffer requirement with different transmission parameters. Finally, the layout area of network interface is about 0.43 mm² based on 0.13 mum CMOS technology.

Keywords

CMOS integrated circuits; high-speed integrated circuits; network interfaces; network-on-chip; CMOS technology; data scrambler; error detect; flow control; high-speed network interface design; inbound traffic; interface function; network-on-chip application; outbound traffic; packet construction; packet-based NoC; peer-to-peer architecture; re-transmission mechanism; serial-link packet-based transmission model; transmission parameters; Communication system traffic control; Data communication; Fabrics; High-speed networks; Network interfaces; Network-on-a-chip; Physical layer; Protocols; System-on-a-chip; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems Proceedings, 2006 International Conference on

Conference_Location

Guilin

Print_ISBN

0-7803-9584-0

Electronic_ISBN

0-7803-9585-9

Type

conf

DOI

10.1109/ICCCAS.2006.285220

Filename

4064467