Analytical Thermal Analysis of On-chip Interconnects

A detailed analytical analysis of the on-chip thermal related problems of interconnects is provided in this paper. By examining and simplifying the power generation mechanism of on-chip devices, compact expressions of the dynamic temperature profile of an interconnect line are derived. It is shown that the temperature profile of the interconnect line has a space-time distribution and thus we propose some new suggestions to floorplanning when considering this effect. The temperature effects on the Power/Ground (P/G) interconnect lines and the Signal interconnect lines are also analyzed. It is shown that the IR drop and the Elmore delay can be increased due to this temperature effect.