• DocumentCode
    3275153
  • Title

    A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation

  • Author

    Timarchi, Somayeh ; Fazlali, Mahmood ; Cotofana, Sorin D.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran, Iran
  • fYear
    2010
  • fDate
    3-6 Oct. 2010
  • Firstpage
    247
  • Lastpage
    252
  • Abstract
    Given that modulo 2n±1 are the most popular moduli in Residue Number Systems (RNS), a large variety of modulo 2n±1 adder designs have been proposed based on different number representations. However, in most of the cases, these encodings do not allow the implementation of a unified adder for all the moduli of the form 2n-1, 2n, and 2n+1. In this paper, we address the modular addition issue by introducing a new encoding, namely, the stored-unibit RNS. Moreover, we demonstrate how the proposed representation can be utilized to derive a unified design for the moduli set {2n-1,2n,2n+1}. Our approach enables a unified design for the moduli set adders, which opens the possibility to design reliable RNS processors with low hardware redundancy. Moreover, the proposed representation can be utilized in conjunction with any fast state of the art binary adder without requiring any extra hardware for end-around-carry addition.
  • Keywords
    adders; encoding; residue number systems; RNS representation; encoding; hardware redundancy; moduli set adder; residue number system; unified addition structure; Adders; Delay; Encoding; Hardware; Logic gates; Program processors; Redundancy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2010 IEEE International Conference on
  • Conference_Location
    Amsterdam
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-8936-7
  • Type

    conf

  • DOI
    10.1109/ICCD.2010.5647761
  • Filename
    5647761