Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization

Modern high performance microprocessors experience substantially lower utilization in many of their structural components. To recover energy efficiency from lower utilization, system architects resort to dynamic voltage frequency scaling (DVFS). In this paper, we demonstrate that dynamic adaptations using DVFS are markedly energy inefficient than techniques that design circuits ground up for lower performance. We propose a novel microarchitecture aware gate sizing and threshold voltage assignment algorithm to mitigate this current limitation. Our technique is the first of its kind that exploits architectural slack in gate sizing, and leverages on-chip redundancy and slack. We evaluate this circuit-architectural co-optimization framework in a superscalar processor by combining standard cell based gate sizing flows with state-of-the-art architectural simulation. Our results show 17-46% improvement in the datapath energy efficiency over traditional circuit designs incorporating DVFS schemes.