Title :
VLSI implementation of the CORDIC algorithm using redundant arithmetic
Author :
Dawid, Herbert ; Meyr, Heinrich
Author_Institution :
Aachen Univ. of Technol., Germany
Abstract :
A novel method for computation of the CORDIC (coordinate rotation digital computer) algorithm is presented that is especially well suited for high throughput real-time signal processing applications. A transformation of the original CORDIC algorithm is derived which results in a partially fixed iteration sequence no longer dependent on intermediate signals. The transformed CORDIC iteration is efficiently realized using redundant number systems. The resulting carry-save architecture employing absolute value computation is described. A CORDIC processor for vector rotations (rotation mode) using the transformed CORDIC iteration with a clock frequency of 100 MHz is presented. Due to the extremely high throughput, it is especially well suited for real-time signal processing applications. To the authors´ knowledge this circuit is currently fastest realization of the CORDIC algorithm
Keywords :
CMOS integrated circuits; VLSI; carry logic; digital arithmetic; digital signal processing chips; iterative methods; parallel algorithms; parallel architectures; pipeline processing; real-time systems; redundancy; signal processing; 100 MHz; CORDIC algorithm; CORDIC processor; DSP; VLSI implementation; absolute value computation; carry-save architecture; coordinate rotation digital computer; high throughput; partially fixed iteration sequence; real-time signal processing; redundant arithmetic; rotation mode; transformed CORDIC iteration; vector rotations; Arithmetic; Circuits; Clocks; Computer architecture; Delay; Force control; Frequency; Signal processing algorithms; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230290
