Title :
Parametric study of warpage of PWB assemblies and PWB assembly warpage minimization by component layout optimization
Author :
Ding, Hai ; Ume, I. Charles
Author_Institution :
Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Out-of-plane displacement (warpage) has been a major concern for board-level electronic packaging. Warpage occurred during surface-mount assembly processes and normal operation causes many failures such as misregistration, delamination, die cracks, solder fatigue, and solder opening. Warpage results from a combination of material, geometry, and process effects. In the case of printed wiring board assembly (PWBA), component layout plays a crucial role. Many material, geometry, and process related parameters contribute to PWBA warpage. In this paper, a systematic design of experiments (DOE) is conducted so that the modeling results incorporate all relevant individual and interacting parametric effects, and so that the subsequent data analysis is computationally efficient. Subsequently, the parameters are optimized within practical range to achieve the minimum warpage. Component layout effect on PWBA warpage is also investigated. It is assumed that the materials and dimensions of the printed wiring board (PWB) as well as the components are fixed. The objective is to identify component layouts on the PWB so that it suffers minimal warpage. Evolutionary structural optimization (ESO) is used where the design domain is meshed to fine finite elements and materials at element locations are removed or grown iteratively according to a preset criterion. In conclusion, PWBA warpage can be minimized by carefully levering material, geometry, and process parameters, as well as component layout design.
Keywords :
circuit layout CAD; circuit optimisation; deformation; delamination; design of experiments; fatigue; finite element analysis; printed circuit layout; printed circuit testing; soldering; PWB assembly warpage minimization; PWB dimensions; PWB materials; PWBA warpage; board-level electronic packaging; component layout design; component layout effect; component layout optimization; computationally efficient data analysis; delamination; die cracks; evolutionary structural optimization; finite element meshed design domain; geometry effects; individual parametric effects; interacting parametric effects; material effects; misregistration; modeling; operation failures; optimized parameters; out-of-plane displacement; printed wiring board assembly; process effects; solder fatigue; solder opening; surface-mount assembly processes; systematic design of experiments; Assembly; Conducting materials; Delamination; Electronics packaging; Fatigue; Geometry; Parametric study; Surface cracks; US Department of Energy; Wiring;
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
DOI :
10.1109/ECTC.2004.1320372