DocumentCode :
3275541
Title :
Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array
Author :
Honkote, Vinayak ; Taskin, Baris
Author_Institution :
Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA
fYear :
2010
fDate :
3-6 Oct. 2010
Firstpage :
209
Lastpage :
214
Abstract :
Rotary clocking is a traveling wave based high-speed resonant clocking technology with low-power and controllable-skew properties. Capacitive load balance and bounded clock skew are identified as the primary requirements to maintain a stable oscillation frequency across the rings and to achieve timing closure, respectively, in the rotary oscillatory array (ROA). Towards this end, two methodologies are proposed to achieve balanced capacitive loads across the rings of the ROA with a bounded skew constraint. Experiments performed on IBM R1-R5 benchmark circuits show a 5.62X improved capacitive balance and a 3.67% improved clock skew to a total skew of 6.55% of the clock period at 1.8GHz. SPICE simulations show that the frequency variation across the rings of the ROA is reduced from 10.14% to 2.12% as well. Power dissipated with the proposed optimization methodologies are within ±1.5% of the conventional design automation techniques for rotary synchronization.
Keywords :
circuit oscillations; electronic design automation; resource allocation; synchronisation; timing circuits; IBM R1-R5 circuits; bounded skew constraint; frequency 1.8 GHz; rotary clocking technology; rotary oscillatory array; rotary synchronization; skew-aware capacitive load balancing; Benchmark testing; Capacitance; Clocks; Oscillators; Registers; Synchronization; Zero current switching;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2010 IEEE International Conference on
Conference_Location :
Amsterdam
ISSN :
1063-6404
Print_ISBN :
978-1-4244-8936-7
Type :
conf
DOI :
10.1109/ICCD.2010.5647781
Filename :
5647781
Link To Document :
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