DocumentCode
3275567
Title
A systolic VLSI architecture for complex SVD
Author
Hemkumar, Nariankadu D. ; Cavallaro, Joseph R.
Author_Institution
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Volume
3
fYear
1992
fDate
10-13 May 1992
Firstpage
1061
Abstract
A systolic algorithm for the SVD (singular value decomposition) of arbitrary complex matrices based on the cyclic Jacobi method with parallel ordering is presented. A novel two-step, two-sided unitary transformation scheme, tailored to the use of CORDIC (coordinate rotation digital computer) algorithms for high-speed arithmetic, is employed to diagonalize a complex 2×2 matrix. Architecturally, the complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An expandable array of O (n 2) complex 2×2 matrix processors computes the SVD of an n ×n matrix in O (n log n ) time. A CORDIC architecture for the complex 2×2 processor with an area complexity twice that of a real 2×2 processor is proposed. Computation time for the complex SVD array is less than three times that for a real SVD array with a similar CORDIC-based implementation
Keywords
VLSI; digital arithmetic; digital signal processing chips; matrix algebra; parallel algorithms; signal processing; systolic arrays; Brent-Luk-VanLoan array; CORDIC architecture; complex SVD array; coordinate rotation digital computer; cyclic Jacobi method; high-speed arithmetic; image processing; parallel ordering; singular value decomposition; systolic VLSI architecture; systolic algorithm; Arithmetic; Computer architecture; Concurrent computing; Jacobian matrices; Matrix decomposition; Signal processing algorithms; Singular value decomposition; Symmetric matrices; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.230297
Filename
230297
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