On the testability of array structures for FFT computation

Author

Lombardi, F. ; Shen, Y.-N. ; Muzio, J.

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA

fYear

1990

fDate

9-13 Dec 1990

Firstpage

519

Lastpage

522

Abstract

Presents new approaches for testing VLSI array architectures used in the computation of the complex N-point Fast Fourier Transform under a single combinational fault model. An unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture. This is accomplished by showing a topological equivalence between the FFT array and a linear (one-dimensional) array

Keywords

VLSI; computer testing; computerised signal processing; fast Fourier transforms; fault tolerant computing; parallel architectures; performance evaluation; FFT computation; Fast Fourier Transform; VLSI array architectures; array structures; combinational fault model; complexity; digital signal processing; fault detection; single cell-level fault model; testability; topological equivalence; Computer architecture; Computer science; Digital signal processing; Fast Fourier transforms; Manufacturing; Pipelines; Process design; Systolic arrays; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on

Conference_Location

Dallas, TX

Print_ISBN

0-8186-2087-0

Type

conf

DOI

10.1109/SPDP.1990.143595

Filename

143595