Title :
A high-performance CABAC encoder architecture for HEVC and H.264/AVC
Author :
Jinjia Zhou ; Dajiang Zhou ; Wei Fei ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
Abstract :
This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%~34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27~4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.
Keywords :
adaptive codes; arithmetic codes; binary codes; data compression; high definition television; video coding; BPBS; CABAC architecture; H.264-AVC format; HEVC format; HPC; SDT scheme; bypass bin splitting scheme; clock rate; dual-standard binarization design; high-performance CABAC encoder architecture; high-performance context adaptive binary arithmetic coding architecture; hybrid path coverage scheme; next-generation UHDTV applications; prenormalization; real-time UHDTV encoding; state dual-transition scheme; video encoder chip; CABAC; HEVC; UHDTV; entropy coding;
Conference_Titel :
Image Processing (ICIP), 2013 20th IEEE International Conference on
Conference_Location :
Melbourne, VIC
DOI :
10.1109/ICIP.2013.6738323