Clock-feedthrough compensated switched-capacitor circuits

Novel switched-capacitor circuits are presented which greatly suppress the clock-feedthrough effect. The principle is based on the cancellation of feedthrough charges stored in two capacitors. The circuit operations are also insensitive to parasitic capacitances and offset voltages of op-amps, and thus allow an accurate analog signal processing. As a typical example, a cyclic analog-to-digital converter is proposed. Error analyses show that a resolution higher than 12 bits is attainable by implementing the architecture using presently available CMOS technologies. Experimental waveforms are also given to confirm the principles of operation