Optimizing the output impedance of a power delivery network for microprocessor systems

Author

Mandhana, Om P.

Author_Institution

Somerset Design Center, Motorola Inc., Austin, TX, USA

Volume

2

fYear

2004

fDate

1-4 June 2004

Firstpage

1975

Abstract

This paper presents a systematic design oriented frequency domain analysis of a multi-stage power distribution network. (PDN) of a microprocessor system with the power source represented as,a close-loop small-signal model of a dc to dc, converter. Generalized analytical expressions are derived for the output impedance including voltage sensing at different, stages. of, the multistage PDN. The affect of optimally selecting the ESR, ESL and capacitance of the decoupling capacitors at different stages of the PDN is described in terms of the converter´s loop gain, crossover frequency, phase margin and their impact on realizing the flat output impedance at the microprocessor core. Simulation results are presented to support the validity of the novel design oriented analysis.

Keywords

DC-DC power convertors; electric impedance; equivalent circuits; frequency-domain analysis; lumped parameter networks; microprocessor chips; power supply circuits; transfer functions; DC-DC converter; close-loop small-signal model; crossover frequency; decoupling capacitors; design oriented frequency domain analysis; loop gain; lumped equivalent model; microprocessor system; multistage power distribution network; output impedance; phase margin; power delivery network; power integrity; Capacitance; Capacitors; Frequency conversion; Frequency domain analysis; Impedance; Microprocessors; Paramagnetic resonance; Power system modeling; Power systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2004. Proceedings. 54th

Print_ISBN

0-7803-8365-6

Type

conf

DOI

10.1109/ECTC.2004.1320398

Filename

1320398