A design of reconfigurable bus based on the embedded microprocessor SIMD core

A data parallel computer architecture model based on the reconfigurable bus is proposed. First, for the problems existing in the modern multimedia processing, one dimensional processing element array architecture based on the reconfigurable bus is put forward; secondly, the communication module and the data transmission mode between each processing element are designed, namely, a design based on a reconfigurable bus; finally, test and verification of several commonly-used image processing algorithms indicate that one dimensional SIMD architecture based on the reconfigurable bus is logically feasible.