Testable design of bit-level systolic block FIR filters

A design-for-testability approach for VLSI cellular arrays, based on M-testability conditions, is applied to bit-level systolic block FIR (finite impulse response) filters. M-testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. The authors illustrate this approach on bit-level systolic arrays which implement block FIR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size