Title :
A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications
Author :
Poornaiah, D.V. ; Mohan, P. V Ananda
Author_Institution :
Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India
Abstract :
In this paper, an efficient algorithm for concurrent computation of two real multiplications and/or two real additions usually required for high-throughput image and video coding applications is described. The proposed algorithm is mapped onto a novel concurrent dual multiplier-dual adder cell based on carry-save 4:2 compressors. A detailed performance analysis of the the proposed cell shows reductions ranging from 15% to 60% in the computation time and area when compared with the conventional processing elements making it highly attractive for VLSI implementation
Keywords :
VLSI; adders; computational complexity; data compression; digital signal processing chips; multiplying circuits; video coding; VLSI; carry-save 4:2 compressors; computation time; concurrent dual multiplier-dual adder architecture; high-throughput image coding; video coding applications; Additives; Compressors; Logic design; Minimization methods; Pulse inverters; Signal design; Signal processing algorithms; Very large scale integration; Video coding; Video signal processing;
Conference_Titel :
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7228-5
DOI :
10.1109/ICVD.1996.489458