Title :
High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath
Author :
Fard, Saeed Fouladi ; Alimohammad, Amirhossein ; Cockburn, Bruce ; Schlegel, Christian
Author_Institution :
Ukalta Eng., Edmonton, AB, Canada
Abstract :
In this paper we introduce an especially compact architecture for the high-throughput simulation of Rayleigh fading channels and hence the verification of high path count wireless systems at hardware speeds. The new architecture utilizes a time-multiplexed scheme that allows the fading channel simulator to be fit into a small fraction of a field-programmable gate array (FPGA). Implementing a 64-path fading channel simulator on a Xilinx Virtex-II Pro XC2VP100-6 FPGA uses only 29% of the configurable slices, 2% of the block memories, and 1% of the dedicated multipliers, while generating 64Ã238 million complex-valued fading samples per second.
Keywords :
Rayleigh channels; field programmable gate arrays; Rayleigh fading channel simulator; Xilinx Virtex-II Pro XC2VP100-6 FPGA; block memories; field-programmable gate array; high path count wireless systems; high-throughput simulation; time-multiplexed datapath; Communication channels; Computational modeling; Data engineering; Fading; Field programmable gate arrays; Frequency; Hardware; MIMO; Rayleigh channels; Wireless communication;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398008