Pushing the performance limits due to power dissipation of future ULSI chips

Author

Noll, T.G. ; de Man, E.

Author_Institution

Siemens Corp. Res. & Dev., Munich, Germany

Volume

4

fYear

1992

fDate

3-6 May 1992

Firstpage

1652

Abstract

The trend of power dissipation in current and future commercial CMOS integrated circuits is investigated considering that the minimum device size may scale down to about 0.1 μm in the next decade. The power dissipation trend makes clear that it will be necessary to come up with some new concepts to reduce the power dissipation of future chips by an order of magnitude. The possibilities for doing this are analyzed on the architectural, logical, and layout level of the implementation. It is shown that pipelining is an attractive way of parallelization enforcing localization and short critical paths which are necessary to keep the power dissipation low. Approaches to reduce the power dissipation of the clock system in high-performance chips are discussed

Keywords

CMOS integrated circuits; VLSI; clocks; digital integrated circuits; integrated circuit technology; 0.1 micron; CMOS integrated circuits; ULSI chips; architectural level; clock system; layout level; logical level; minimum device size; parallelization; performance limits; pipelining; power dissipation; short critical paths; CMOS technology; Capacitance; Circuits; Clocks; Delay; Frequency; Power dissipation; Silicon; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230360

Filename

230360