A micropower analog hearing aid on low voltage CMOS digital process

Author

Bhattacharyya, A.B. ; Rana, R.S. ; Guha, S.K. ; Bah, R. ; Anand, Sneh ; Zarabi, M.J. ; Govindacharyulu, P.A. ; Gupta, Vivek ; Mohan, Vivek ; Roy, Jatin ; Atri, Amul

Author_Institution

Indian Inst. of Technol., New Delhi, India

fYear

1996

fDate

3-6 Jan 1996

Firstpage

85

Lastpage

89

Abstract

A two-chip analog micropower hearing aid circuit is developed which is based on a low voltage three micron CMOS process. The novel features of the circuit are the use of adaptive biasing of MOS Translinear Loop (MTL) circuit and an innovative application of an adaptive technique in reducing the value of a degenerating linearising resistor in the input differential stage of the AGC block. The above two measures enable reduction of power consumption and external component count. Class-D amplifier provides high conversion efficiency at the output stage. The proposed configuration is now under integration for developing a one chip general purpose CMOS analog hearing aid with capability to operate with 1.0 volt supply voltage

Keywords

CMOS analogue integrated circuits; automatic gain control; differential amplifiers; hearing aids; 1.0 V; 3 micron; AGC block; MOS translinear loop circuit; adaptive biasing; conversion efficiency; degenerating linearising resistor; input differential stage; low voltage CMOS digital process; micropower analog hearing aid; power consumption; Auditory system; CMOS analog integrated circuits; CMOS process; CMOS technology; Gain control; Hearing aids; Low voltage; Preamplifiers; Pulse amplifiers; Pulse width modulation inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1996. Proceedings., Ninth International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-8186-7228-5

Type

conf

DOI

10.1109/ICVD.1996.489462

Filename

489462