An Efficient VLSI Implementation of Distributed Architecture for DWT

This paper proposes an efficient and simple architecture for 9/7 discrete wavelet transform based on distributed arithmetic. To derive new proposed architecture, we consider the periodicity and symmetry of DWT to optimize the performance and reduce the computational redundancy. The inner product of coefficient matrix of DWT is distributed over the input by careful analysis of input, output and coefficient word lengths. In the coefficient matrix, linear maps are used to assign the necessary computation to processing elements in space domain. Moreover, the proposed architecture has regular data flow, and low control complexity. The result is a low hardware complexity DWT processor for 9/7 transforms, which allows two times faster clock than the direct implementation. This design is very suitable for image compression systems, e.g., JPEG2000 and MPEG4