Title :
A reconfigurable co-processor for GMM-based classifier
Author :
Wang, Wei ; Liang, Weiqian
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
This paper presents an efficient and reconfigurable co-processor to calculate Mahalanobis distance, which is the most computation-intensive part in the GMM (Gaussian Mixture Models)-based classifier. The Mahalanobis distance´s calculation is divided into three parts (vector-vector subtraction, matrix-vector multiplication, and vector-vector multiplication) and these three parts can operate in a parallel way. The proposed architecture was implemented in Xilinx FPGA XC5VLX110T. Tested with a 358-state 3-mixture 39-feature 800-word HMM, co-processor operates at 35MHz to meet real-time requirement of speech recognition.
Keywords :
Gaussian distribution; coprocessors; pattern classification; reconfigurable architectures; 358-state 3-mixture 39-feature 800-word HMM; GMM-based classifier; Gaussian mixture models; Mahalanobis distance; Xilinx FPGA XC5VLX110T; frequency 35 MHz; hidden Markov model; matrix-vector multiplication; reconfigurable co-processor; speech recognition; vector-vector multiplication; vector-vector subtraction; Computer architecture; Coprocessors; Field programmable gate arrays; Hardware; Hidden Markov models; Microelectronics; Pattern recognition; Speech recognition; Symmetric matrices; Very large scale integration;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398026
