Title :
Synchronous controller models for synthesis from communicating VHDL processes
Author :
Narasimhan, Naren ; Roy, Jay ; Vemuri, Ranga
Author_Institution :
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Abstract :
VHDL permits design descriptions with communicating multiple processes and provides signal assignments and wait statements to facilitate coordination and communication among the processes. These constructs lead to concise behavioral specifications but make controller generation in high level synthesis difficult. Current work on synthesis from VHDL restricts the behavioral subset, excluding or limiting the use of some of these constructs, thus leading to simple controller structures. Our paper proposer a controller model based on multiple, synchronous, communicating finite state machines. The proposed controller model permits the use of multiple processes with signal assignments and wait statements in behavioral specifications
Keywords :
control system CAD; control systems; controllers; finite state machines; hardware description languages; high level synthesis; VHDL; behavioral specifications; communicating multiple processes; finite state machine; high level synthesis; signal assignments; synchronous controller model; wait statements; Automata; Clocks; Encoding; High level synthesis; Scheduling; Signal design; Signal generators; Signal processing; Signal synthesis; Throughput;
Conference_Titel :
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7228-5
DOI :
10.1109/ICVD.1996.489484