Title :
Clocked semi-floating-gate ultra low-voltage inverting current mirror
Author :
Berg, Y. ; Mirmotahari, O.
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present a low voltage inverting current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits. By applying offsets to semi-floating-gate nodes the current level may be increased compared to non-floating-gate design applying ultra low supply voltages. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed inverted current mirror can operate at supply voltages below 250 mV. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.
Keywords :
CMOS logic circuits; MOSFET; current mirrors; Spectre simulator; clocked semifloating-gate transistors; effective threshold voltage; low-voltage digital CMOS circuits; nonfloating-gate design; offset voltages; semifloating-gate nodes; size 90 nm; supply voltages; ultra low supply voltages; ultra low-voltage inverting current mirror; Analog circuits; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Dynamic voltage scaling; Inverters; Low voltage; Mirrors; Threshold voltage;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398036
