DocumentCode :
3277055
Title :
Thermal behavior of a soldered Cu-Si interface
Author :
Van Heerden, D. ; Rude, T. ; Newson, J. ; Knio, O. ; Weihs, T.P. ; Gailus, D.W.
Author_Institution :
Reactive NanoTechnologies Inc., Hunt Valley, MD, USA
fYear :
2004
fDate :
9-11 Mar 2004
Firstpage :
46
Lastpage :
49
Abstract :
The thermal behavior of a reactively soldered interface between a Cu heat sink and a Si die is analyzed experimentally. Two aspects are addressed, thermal fatigue of these joints, and the survival of the circuitry on the die during joining. In the reactive soldering process a multilayered reactive NanoFoil™ acts as a heat source for melting the solder during joining. The foils consists of hundreds of alternating nanoscale layers of Ni and Al, and supports controlled self-propagating reactions that can be initiated in air and at room temperature. The nanostructured reactive multilayered foils (NanoFoils) are designed to minimize thermal exposure of the components as well as residual stress. To study thermal fatigue of reactively soldered Cu-Si joints three populations of samples are studied, one fabricated using conventional soldering techniques, and two reactively soldered populations fabricated using different solder thicknesses. Both the conventionally and reactively soldered samples consist of a stack composed of two Cu blocks with a Si die soldered between them. The difference between these two types of samples is that for the conventionally soldered joints the heat source used for melting the solder is an oven, while for the reactively soldered joints a nanostructured reactive multilayered foil is used. We show that neither the conventionally soldered samples nor the reactively soldered populations exhibit significant degradation of thermal performance after 1000 cycles between 25 °C and 125 °C. In addition we show that a commercially available bare-die chip package can be successfully reactively bonded with no degradation in the performance of the chip, but does offer significant reduction in die operating temperature during normal operation.
Keywords :
copper; elemental semiconductors; heat sinks; integrated circuit interconnections; semiconductor-metal boundaries; silicon; soldering; thermal resistance; thermal stress cracking; 25 to 125 degC; Cu heat sink; Cu-Si; Si die; heat source; multilayered reactive NanoFoil; reactive soldering process; residual stress; soldered Cu-Si interface; thermal behavior; thermal fatigue; Circuits; Fatigue; Heat sinks; Ovens; Packaging; Residual stresses; Soldering; Temperature control; Thermal degradation; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal Measurement and Management Symposium, 2004. Twentieth Annual IEEE
ISSN :
1065-2221
Print_ISBN :
0-7803-8363-X
Type :
conf
DOI :
10.1109/STHERM.2004.1291300
Filename :
1320451
Link To Document :
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