DocumentCode
3277129
Title
LUT-based FPGA technology mapping using permissible functions
Author
Suyama, Takayuki ; Sawada, Hiroshi ; Nagoya, Akira
Author_Institution
NTT Commun. Sci. Lab., Kyoto, Japan
fYear
1996
fDate
3-6 Jan 1996
Firstpage
215
Lastpage
218
Abstract
In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs
Keywords
Boolean functions; application specific integrated circuits; combinational circuits; field programmable gate arrays; logic CAD; multivalued logic circuits; table lookup; LUT-based FPGA; initial mapping; loop-free multilevel combinational circuit; minimized circuit; n-variable Boolean function; permissible functions; technology mapping; Application specific integrated circuits; Boolean functions; Combinational circuits; Costs; Field programmable gate arrays; High level synthesis; Laboratories; Programmable logic arrays; Slabs; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-8186-7228-5
Type
conf
DOI
10.1109/ICVD.1996.489487
Filename
489487
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