DocumentCode :
3277667
Title :
Functional verification of EPA chip
Author :
Li, Qiu ; Dong-qin, Feng
Author_Institution :
Inst. of Cyber-Syst. & Control, Zhejiang Univ., Hangzhou, China
fYear :
2011
fDate :
15-17 April 2011
Firstpage :
4216
Lastpage :
4220
Abstract :
This paper presents a new verification method exercised on EPA chip. This method is to build a coverage-driven functional verification testbench, with constraint random stimulus and direct stimulus. The hierarchical testbench, which is developed based on Open Verification Methodology (OVM), is reusable and efficient. Compared to traditional verification methods, it´s proved that this new one has greatly saved verification time and manpower, enhanced verification unit reuse.
Keywords :
formal verification; local area networks; microprocessor chips; EPA chip; Ethernet; constraint random stimulus; coverage-driven functional verification; direct stimulus; hierarchical testbench; open verification methodology; plant automation; verification unit reuse; Computers; Frequency modulation; IP networks; Manuals; Payloads; System-on-a-chip; EPA; constraint random; coverage-driven; functional verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electric Information and Control Engineering (ICEICE), 2011 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-8036-4
Type :
conf
DOI :
10.1109/ICEICE.2011.5777483
Filename :
5777483
Link To Document :
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