High throughput architecture for CLICHÉ Network on Chip

High throughput chip-level integration of communicating heterogeneous elements (CLICHE) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of high throughput CLICHE¿ switch is decreased by 18% as compared to CLICHE¿ switch. The total metal resources required to implement high throughput CLICHE¿ design is increased by 7% as compared to the total metal resources required to implement CLICHE¿ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHE¿ architecture.