Title :
Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips
Author :
Holzer, M. ; Rupp, M.
Author_Institution :
Vienna Univ. of Technol., Vienna
Abstract :
Early performance estimation of a system-on-chip design is a key issue for a successful design methodology. One of the most important parameters is the run time of a function. Especially optimization techniques like hw/sw partitioning rely on those estimations. This paper presents a static analysis method in order to characterize a hardware acceleration unit regarding its run time. The performance of the presented method is shown on several examples from the embedded systems area and compared to results from high level synthesis.
Keywords :
embedded systems; hardware-software codesign; integrated circuit design; system-on-chip; embedded systems; execution time estimation; hardware acceleration unit; hw-sw partitioning; static analysis method; system-on-chip design; Costs; Delay; Design methodology; Field programmable gate arrays; Hardware; High level synthesis; Signal processing algorithms; Software algorithms; System-on-a-chip; Timing;
Conference_Titel :
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
0-7803-9294-9
DOI :
10.1109/ISSOC.2005.1595645
