DocumentCode :
3278068
Title :
Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures
Author :
Rivaton, Arnaud ; Quevremont, Jerome ; Zhang, Qiwei ; Wolkotte, Pascal ; Smit, Gerard
Author_Institution :
Thales Commun., Colombes
fYear :
2005
fDate :
17-17 Nov. 2005
Firstpage :
74
Lastpage :
77
Abstract :
To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT´S XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a fast Fourier transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.
Keywords :
broadcasting; fast Fourier transforms; reconfigurable architectures; reduced instruction set computing; telecommunication computing; Montium; XPP technology; coarse-grain reconfigurable architectures; dual ARM9 RISC core architecture; fast Fourier transform; low-power digital broadcasting; nonpower-of-two FFT; Fast Fourier transforms; Flexible printed circuits; Logic arrays; Microcontrollers; Power dissipation; Reconfigurable architectures; Reduced instruction set computing; Runtime; Signal processing algorithms; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
0-7803-9294-9
Type :
conf
DOI :
10.1109/ISSOC.2005.1595648
Filename :
1595648
Link To Document :
بازگشت