High speed Reed-Solomon decoder with pipeline architecture

Quality of service (QoS) is one of the most important factors in mobile communication networks. Decreasing of delay, including processing time, and error correction are proposed to get higher QoS in mobile networks. Reed-Solomon coding is one of the most important schemes for this purpose, for error correction. In this paper a pipeline approach of RS decoder is proposed to reduce the processing time. In the pipeline architecture of Reed-Solomon decoder two schemes are proposed, first the Reed-Solomon decoder is developed in five stages pipeline, then to reduce the data dependencies between stages, it is developed by three stages pipeline. Because of the data dependency between the stages, it is impossible to achieve ideal speedup. In the five-stage pipeline scheme of RS decoder the data dependency has been caused the %18.5 loss in the speedup, this value for the three-stage pipeline scheme is about %14. The hardware description language (HDL) method is employed to hardware synthesis the Reed-Solomon decoder on FPGA chips.