• DocumentCode
    3278168
  • Title

    SoC Leakage Power Reduction Algorithm by Input Vector Control

  • Author

    Chang, Xiaotao ; Fan, Dongrui ; Han, Yinhe ; Zhang, Zhimin

  • Author_Institution
    Chinese Acad. of Sci., Beijing
  • fYear
    2005
  • fDate
    17-17 Nov. 2005
  • Firstpage
    86
  • Lastpage
    89
  • Abstract
    Input vector control is an effective method to reduce leakage power when a circuit enters sleep mode. It seeks to find a vector that minimizes leakage power to be statically applied to the primary inputs of a circuit. This paper presents a fast algorithm to search the input vector which can lead to the minimal leakage power. In order to accelerate the evaluation procedure, the circuit under simulation is reduced by circuit partition based on the signal probability model first. Then, a searching algorithm based on sub-circuit is used to find the target input vector. Experimental results on large combinational circuits of ISCAS85 benchmark and a real general-purpose SoC show this algorithm can accelerate calculation over three times with acceptable accuracy (error about 0.14%).
  • Keywords
    combinational circuits; electrical faults; integrated circuit modelling; low-power electronics; probability; search problems; system-on-chip; ISCAS85 benchmark; SoC leakage power reduction algorithm; input vector control; searching algorithm; signal probability; Acceleration; Circuit simulation; Combinational circuits; Computers; Dynamic voltage scaling; Leakage current; Partitioning algorithms; Power dissipation; Registers; Threshold voltage; SoC; gate-level simulator; input vector control; leakage power; low power design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip, 2005. Proceedings. 2005 International Symposium on
  • Conference_Location
    Tampere
  • Print_ISBN
    0-7803-9294-9
  • Type

    conf

  • DOI
    10.1109/ISSOC.2005.1595651
  • Filename
    1595651