DocumentCode :
3278225
Title :
Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration
Author :
Lee, Jae-Gon ; Ahn, Ki-Yong ; Kyung, Chong-Min
Author_Institution :
Korea Advanced Inst. of Sci. and Technol., Daejeon
fYear :
2005
fDate :
17-17 Nov. 2005
Firstpage :
100
Lastpage :
103
Abstract :
We can overcome performance limitation imposed by limited throughput of simulator-accelerator channel by introducing predictive channel access techniques. Predictive channel access technique minimizes the number of channel access by allowing execution of either simulation or acceleration domain and predicting responses of the other domain. While this method can bring a lot of performance gain when prediction accuracy is high, it can also result in bad performance when prediction accuracy is low. We call it performance deterioration of predictive method. This paper shows an adaptive predictive synchronization scheme where the "aggressiveness" of prediction is calibrated according to the environment. This eliminates performance deterioration and brings high performance with good prediction accuracies and moderate performance even when prediction accuracy is low.
Keywords :
synchronisation; system-on-chip; SoC; adaptive predictive synchronization scheme; predictive channel access techniques; simulator-accelerator channel; Acceleration; Accuracy; Buffer storage; Clocks; Discrete event simulation; Microarchitecture; Performance gain; Predictive models; Testing; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
0-7803-9294-9
Type :
conf
DOI :
10.1109/ISSOC.2005.1595654
Filename :
1595654
Link To Document :
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