An Effective IP Reuse Methodology for Quality System-on-Chip Design

Intellectual property (IP) reuse improves system-on-a-chip (SoC) design productivity, and helps to meet design quality and time-to-market goals. However, IP quality issues in terms of inadequate test coverage, low power capability, absence of functional features etc. has led to reduced benefits from reuse. This is because the IP is usually designed for use in one chip and later on (re)used in chips having different requirements. Hence, part of SoC design productivity is spent in enhancing the IP to the desired quality level. As updated versions of the IP may be released several times during the SoC design phase, managing the design database poses challenge with respect to the IP enhancements. In this paper, we describe the methodology that we successfully followed in our SoC design. It consists of enhancing the IPs for meeting the desired goals, validating the changes and controlling its version in the design database. It is required to integrate three mission critical IPs developed by the customer. Certain modifications to the customer IPs were called for to meet SoC design goals and obtain a better quality of implementation.