Title :
An active analog delay and the delay reference loop
Author :
Buckwalter, James ; Hajimiri, Ali
Author_Institution :
Califomia Inst. of Technol., Pasadena, CA, USA
Abstract :
Wireline signal processing circuits such as transversal equalizers rely on true time delay. An active analog delay stage is proposed that requires a sixteenth of the area of a comparable LC delay line. A delay reference loop is also presented to tune the delay stage against process, voltage, and temperature variations. A reference signal is introduced to tune the delay. The impact of non-idealities must be considered, to understand the relationship between the reference frequency and the locked time delay. A SiGe BiCMOS implementation of the active analog delay stage and delay reference loop is presented that operates to 10 Gb/s.
Keywords :
BiCMOS analogue integrated circuits; Ge-Si alloys; active networks; delay circuits; equalisers; semiconductor materials; 10 Gbit/s; BiCMOS implementation; SiGe; active analog delay stage; channel equalization; delay locked loop; delay reference loop; delay tuning reference signal; process/voltage/temperature variations; reference frequency/locked time delay relationship; tapped-delay lines; transversal equalizers; true time delay; Circuits; Delay effects; Delay lines; Equalizers; Frequency; Germanium silicon alloys; Signal processing; Silicon germanium; Temperature; Voltage;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE
Print_ISBN :
0-7803-8333-8
DOI :
10.1109/RFIC.2004.1320512