Interfacing UML 2.0 for Multiprocessor System-on-Chip Design Flow

Author

Riihimäki, Jouni ; Kukkala, Petri ; Kangas, Tero ; Hännikäinen, Marko ; Hämäläinen, Timo D.

Author_Institution

Nokia Technol. Platforms, Tampere

fYear

2005

fDate

17-17 Nov. 2005

Firstpage

108

Lastpage

111

Abstract

UML 2.0 can be extended for embedded system design. Our solution is a well-defined modeling approach, known as TUT-profile, for UML 2.0 together with our system-on-chip architecture exploration tools. The two major novel features are an explicit control of real-time constraints at UML level and the transformation of the original UML model using back-annotated results of SoC architecture exploration. In this way, all information is kept up to date in a single UML model, in contrary to other flows that use UML only as a front end. This paper focuses on the interface between UML model and the architecture exploration and presents conversions, tools, and intermediate format required for the flow.

Keywords

Unified Modeling Language; embedded systems; integrated circuit design; system-on-chip; SoC architecture exploration; TUT-profile; UML 2.0; embedded system design; multiprocessor system-on-chip design flow; Automatic control; Chip scale packaging; Embedded system; Environmental management; Hardware; High level languages; Logic design; Multiprocessing systems; Process design; Unified modeling language;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2005. Proceedings. 2005 International Symposium on

Conference_Location

Tampere

Print_ISBN

0-7803-9294-9

Type

conf

DOI

10.1109/ISSOC.2005.1595656

Filename

1595656