Architectural and Physical Design Optimizations for Efficient Intra-tile Communication

Intra-tile communication requirements for future SoC platforms are becoming ever more demanding for new processor and memory architectures. Increased bandwidth, low latency and low energy consumption are required, which the current communication architecture solutions cannot provide. In this paper we propose the use of software- controlled, light-weight segmented buses to implement the communication between the processing elements and their working memories. We show that significant energy and delay/latency gains can be expected from the use of this communication architecture.