Enhancing delay fault testability for iterative logic arrays

Iterative logic arrays are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. Therefore, in order to improve the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as the sequential fault models and the delay fault models should also be considered. Therefore, delay fault testability conditions are proposed for iterative logic arrays (ILAs) in this paper. Our approach applies to ILAs with an arbitrary dimension, e.g., linear and mesh-connected ILAs, etc. Moreover, it can also be applied to various other connection types, e.g., butterfly-connected and shuffle-connected ones. A design for-testability approach is used to make these arrays delay fault testable based on the proposed testability conditions. To illustrate our approach, we give a delay fault testable FFT processor as an example and show that an overhead of no more than 5% is sufficient to make it C-testable. It requires only 128 2-pattern tests to achieve 100% cell-delay-fault coverage regardless of the word length and the computation points of the FFT processor. Our approaches also guarantee that the test set is easy to generate, and the corresponding BIST structure requires smaller hardware overhead and has a more regular structure.