Title :
SoC framework for FPGA: A case study of LTE PUSCH receiver
Author :
Demirsoy, Suleyman S. ; Marks, Kellie
Author_Institution :
Altera Eur. Ltd., High Wycombe, UK
Abstract :
An SoC framework is presented, comprising of a plug-and-play infrastructure where the system communication is abstracted from the processing elements. A software scheduler is used with a hardware modelling environment for latency analysis. Using the framework, an LTE uplink data channel (PUSCH) receiver design is shown to meet the stringent latency targets.
Keywords :
field programmable gate arrays; integrated circuit design; integrated circuit modelling; scheduling; system-on-chip; FPGA; LTE PUSCH receiver; LTE uplink data channel; PUSCH receiver design; SoC framework; hardware modelling environment; latency analysis; plug-and-play infrastructure; software scheduler; Communication networks; Communication system control; Computer aided software engineering; Control systems; Delay; Distributed control; Field programmable gate arrays; Hardware; Network interfaces; Network-on-a-chip;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398103
